Cache Simulation Project

I have half of the code from professor it should be completed with that no code from Github. Direct Mapping must be completed. I am not able to add code here so i will just add the whole word document. 


Get Help With a similar task to - Cache Simulation Project

Login to view and/or buy answers.. or post an answer
Additional Instructions:

Cache Simulation Program CSIS 5814 Spring 2020 For this project you will create a data cache simulator. The main reason for this simulator is to use it to determine optimal parameters for a given access sequence. As in your previous project, this project has several levels of complexity. The lowest level is a simple direct mapped read-only data cache. Higher levels include set associative and fully associative caches. The rest of this discussion here will focus on the levels above the minimum. The simulator you implement needs to work for an N-way set associative cache which can be of arbitrary size (in power of 2) up to 64KB total size. You should assume the memory is byte addressable. The input to your simulator should be a file named addresses.dat. Your simulator will have to read a series of memory addresses from the file. Each line in the file contains a character 'r' or 'w', white spaces, and a positive decimal integer representing an address. If you are not implementing a writeable cache, your program should ignore the lines that starts with a 'w'. For each address, you should model the reading/writing a byte from the simulated cache, recording a hit or a miss. For this assignment, it does not matter what data is read or written, so you do not have to model actual memory. Your simulator need to support the following three command line parameters (use int main (argc, argv[])): -s Cache Size (in Bytes) -a Associativity (not needed for direct mapped) -b Block size (in Bytes) All three values should be integer powers of 2. All sizes are in Bytes. A version of the addresses.dat is available. For Set-Associative and Fully-Associative models, use the Round Robin replacement policy for choosing the cache block to be replaced in the set, If you are implementing a writable cache, always choose a clean block before choosing a dirty block. Assume a Write Allocate policy when writing to a block that is not in cache. I have designed three classes that your program must be based on. They are: a single cache entry CacheEntry.h CacheEntry.cc (complete) a cache set CacheSet.h CacheSet.cc (partial) a cache Cache.h (coming) Cache.cc (partial) (coming) Your simulator will have to read a series of memory addresses from the file addreses.dat which Your program must be able to run on the departmental server (gemini.csis.ysu.edu). Program output The output of your simulator should look like: >cache-sim -s 1024 -b 32 -a 2 cache size: 1024 bytes block size: 32 bytes associativity: 2 total loads: (depends on data) total writes: (depends on data/level of project) cache hits: (depends on data) cache misses: (depends on data) miss rate: (depends on data) The maximum values your simulator needs to support is 65536 for the cache size, 256 bytes for the block size, and full associativity (size/block size). Report: In addition to your program, you must turn in a written report. Your report must include three line graphs. The Y-axis will be the miss rate. The X-axis will vary as follows: 1. The X-axis will be the size of the cache (given a fixed block size of 32 bytes and fixed associativity of 4). Your cache sizes should be 1KB, 2KB, 4KB, 8KB, 16KB, 32KB, and 64KB. 2. The X-axis will be the block size of the cache (given a fixed cache size of 8192 bytes and fixed associativity of 4). Your cache block sizes should be 1, 2, 4, 8, 16, 32, and 64 bytes. 3. The X-axis will be the associativity of the cache (given a fixed cache size of 8192 bytes and a fixed block size of 32 bytes). Your associativity should be 1, 2, 4, 8, 16, 32, and fully associative. Grading This project has 4 levels of complexity: Level Mapping Read/Write Replacement Policy Write Policy 0 Direct Read only NA NA 1 Set Associative Read only LRU NA 2 Set Associative Read and Write LRU Write through Completion of level 0 of this project will result in an 80% on project grade for the course. By completing additional levels, the project grade can be affected as follows: Level completed Max grade on project Undergraduate Graduate and Honors level 0 70% 60% level 1 90% 80% level 2 115% 100%

Related Questions

Similar orders to Cache Simulation Project
32
Views
0
Answers
Advance topics in machine learning (Kernels) 2 questions.
Any 2/3 Questions need answering on Advance topics in machine learning (Kernels). relevant notes can be shared upon request....
17
Views
0
Answers
Using R programming to perform functions and do work.
The expectations are to use R programming to answer the questions attached the file, and the result is also to be a .r file....
13
Views
0
Answers
write up a report using c programming.
Using the knowledge acquired from this module write a descriptive report to solve the programming problems listed below. The word count limit is 500 words You must include the full code implementation as appendix! I recommend you use Courier New size 1...
16
Views
0
Answers
Analyse requirements and select appropriate solutions. Design programmes that use appropriate data structures
The assignment requires you to select and implement appropriate data structures, design and implement algorithms and create the relevant software applications that will allow a user to store, update and manipulate the data relating to the operations of an...